1. Field of the Invention
The present invention relates to a demodulator for digital communication, and more particularly, to an In-phase/Quadrature-phase (I/Q) demodulator having an optimized hardware design, and a method of generating an I/Q signal using the optimized hardware.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional I/Q demodulator which processes an input signal having a median frequency of f0. When a sampling frequency output from an analog-to-digital (A/D) converter 10 is
      f    S    =            1      T        ,  , the signal after the A/D converter 10 may be expressed by Equation 1. In Equation 1, T is an inverse number of the sampling frequency.s(nT)=I(nT)cos(nf0T)+Q(nT)sin(nf0T)  (1)
Multipliers 20 and 30 multiply the cos and sin to separate the signal, which is output from the A/D converter 10 and expressed by the Equation 1, into I/Q signals. The median frequency f0 of the signal s(nT) falls to the baseband.
The signal generated by multiplying the Equation 1 by cos is expressed by Equation 2, and the signal generated by multiplying the Equation 1 by sin is expressed by Equation 3:
                                          1            2                    ⁢                      I            ⁡                          (              nT              )                                      +                              1            2                    ⁢                      I            ⁡                          (              nT              )                                ⁢                      cos            ⁡                          (                              2                ⁢                                  nf                  0                                ⁢                T                            )                                      +                              1            2                    ⁢                      Q            ⁡                          (              nT              )                                ⁢                      sin            ⁡                          (                              2                ⁢                                  nf                  0                                ⁢                T                            )                                                          (        2        )                                                      1            2                    ⁢                      Q            ⁡                          (              nT              )                                      -                              1            2                    ⁢                      Q            ⁡                          (              nT              )                                ⁢                      cos            ⁡                          (                              2                ⁢                                  nf                  0                                ⁢                T                            )                                      +                              1            2                    ⁢                      I            ⁡                          (              nT              )                                ⁢                      sin            ⁡                          (                              2                ⁢                                  nf                  0                                ⁢                T                            )                                                          (        3        )            
Each of the I and Q signals, obtainable by the Equations 2 and 3, passes through low pass filters (LPF) 23 and 33, respectively, for an elimination of a double frequency component 2nf0T. When the sampling frequency fs is 4 times as high as the median frequency f0 of the input signal, the Equation 4 is substituted into Equation 2, deriving Equations 5a and 5b:
                              f          S                =                              4            ×                          f              0                                =                      1            T                                              (        4        )            cos(2nf0/f0T)=cos(nπ/2)=1,0−1,0, . . . n=0,1,2,3,  (5a)sin(2nf0/f0T)=sin(nπ/2)=1,0−1,0, . . . n=0,1,2,3,  (5b)
In Equation 5a, the cos-function is converted into 1, 0, −1, 0, . . . , and in Equation 5b the sin-function is converted into 0, 1, 0, −1, . . . . Accordingly, there is no need to use an NCO 40 for generating a sin value and a cos value, and the multipliers are useable as a mutiplexer.
FIG. 2 shows an example of an I/Q demodulator which uses a multiplexer instead of the multiplier to separate the I and Q signals. The multiplexer is useable where the sampling frequency fs is 4 times as high as the median frequency f0 of the input signal.
The I signal and the Q signal are derived as the input signal is digitalized by the A/D converter 10 and passed through first and second multiplexers 21 and 31, respectively and first and second LPFs 23 and 33, respectively. The multiplexer separates the digitalized signal from the A/D converter 10 into an inphase (I) signal and a quadrature (Q) signal. The first multiplexer 21 obtains the I signal, and the second multiplexer 31 obtains the Q signal.
The first multiplexer 21 multiplies the input data signal sequentially by 1, 0, −1, 0 and thereby outputs the I signal, while the second multiplexer 31 multiplies the input data signal sequentially by 0, 1, 0, −1 and outputs the Q signal. The I and Q signals, which are output from first and second multiplexers 21 and 31, respectively, are filtered through the first and second LPFs 25 and 35, respectively, to eliminate the double frequency component from the I and Q signals. The filtered I and Q signals are 2-decimated by 2-decimation units 25 and 35, respectively.
As described above, output from the A/D converter 10 is divided and input to the I signal area and Q signal area, and the input data signals are multiplied respectively by cos- and sin, generating I and Q signals. LPFs 23, 33 are also provided to eliminate the double frequency component of I and Q signals.
FIG. 3A is a block diagram of a conventional resampling unit. The conventional resampling unit 30 includes an L-upsampling unit 22, an LPF 23, an M-down sampling unit 24 and a 2-decimation unit 25.
The L-upsampling unit 22 and the M-downsampling unit 24 sample the input data signals to obtain a certain form of signals. For example, input data signals of data (0), data (1), data (2), data (3), . . . are upsampled with an upsampling coefficient of L=3 to data (0), 0, 0, data (1), 0, 0, data (2), 0, 0, data (3), . . . and down sampled with a downsampling coefficient of M=3 to data (0), data (1), data (2), data (3), . . . . The up and down sampled signal is 2-decimated by the 2-decimation unit 25. An output signal from the resampling unit 30, L×f_in/M, is the input signal f_in which has been sampled by the L-upsampling unit 22 and the M-down sampling unit 24 and 2-decimated by the 2-decimation unit 25.
FIG. 3B is a block diagram of an I/Q demodulator comprising a resampling unit 100 which incorporates two of the resampling units 30.
Resampling unit 100 generates I and Q signals by the multiplication by first and second multiplexers 21 and 31, respectively, of the data signals output from the A/D converter 10 by cos and sin, respectively.
For the I and Q signals generated as described above with reference to FIG. 1, LPFs 23, 33 are provided to eliminate the signals generated at the double frequency.